As integrated circuits (ICs) are gaining in complexity, their respective testing becomes a significant challenge. Designers of ICs containing millions of transistors have relatively limited time to spare on adding facilities for testing a device during manufacturing, and put most of their efforts in the design of their innovative ideas. However, the device must be eventually tested, and must be manufacturable, and therefore various test schemes are added to the actual design. A common practice is adding connected flip-flops (FFs). The FFs are connected in the manner of a long shift register so as to allow control and/or observation of signals. For this purpose, certain FFs that are part of the actual design are made to be scannable. In many cases a special mode, test mode, is used with a single test clock signal to control the entire shifting of data through a scan shift register. In some cases, multiple such scan paths exist in the IC, making the testing of a chip faster.
A challenge for IC design is to provide the highest fault coverage possible. The higher the fault coverage, the more likely it is for a fault to be detected for a device under test, namely a faulty IC being manufactured. One well known method for determining such coverage is the use of fault simulators. These allow a designer to simulate defects in a circuit and find out whether a given set of test vectors (also known as test patterns) can detect the fault.
Some original work was performed by Sandia Labs and published as early as 1979 by L. H. Goldstein, known as SCOAP which stands for Sandia Controllability/Observability Analysis Program, and defines controllability as the ability to set a pin to a certain state or logic value. It further defines observability as the ability to observe the state or logic value of a pin of a circuit at a primary output.
A fault can be a pin stuck at “0” or a pin stuck at “1”. Thus, each pin may be thought of in terms to two different pin faults. A fault is detected when the actual value on a primary output (when the fault is present) does not correspond with the expected value on that primary output of a fault free circuit. A fault is testable in this sense if the fault can be detected. Fault detection can be achieved by applying to the primary inputs a stimulus (otherwise known as one or more test vectors) that exercises a fault on a particular pin (i.e. controls the pin to 0 for stuck at 1 (S@1) and to 1 for stuck at 0 (S@0)) and propagates the actual value on that pin so that it may be observed on a primary output.
Fault coverage is the extent to which a set of test vectors can detect faults. For example, if a set of test vectors provides 90 percent fault coverage, it can detect 90 percent of all simulated stuck-at-1 and stuck-at-0 faults in the circuit. Heretofore, fault coverage is something that has been determined using fault simulations and therefore has been a post simulation figure that is perfectly accurate in hindsight. Fault simulations, however, are highly demanding on computer resources as well as time.
Key to many prior art solutions is the requirement to use test vectors and simulate the circuit in order to provide an estimation of the fault coverage or generation of test vectors. Such solutions are proposed by Shupe et al. in U.S. Pat. No. 4,937,765, Kimura et al. in U.S. Pat. No. 6,044,214, Duggirala et al. in U.S. Pat. No. 6,269,463, and Akin in U.S. Pat. No. 6,370,492. A more complex solution requiring two circuits, one being a reference circuit, is proposed by Nozuyama in U.S. Pat. No. 6,151,694, where the fault coverage is evaluated based on a comparison between a circuit under test and a reference circuit. Yet another solution increases the achievable fault coverage in a circuit, particularly in gate arrays, by enabling sampling of data within an actual device using a chain of flip-flops, as proposed by How et al. in U.S. Pat. No. 6,223,313. Similarly, Hosokawa et al., in U.S. Pat. No. 292,915, suggest a method for design to provide high fault coverage in the actual device. Another type of a solution is proposed by Scott et al. in U.S. Pat. No. 6,059,451, where the fault coverage is determined based on the fault detection probability of each node, which is determined based on the signal probability and transfer probability for each node in a netlist.
It would be advantageous to be able to estimate the potentially achievable fault coverage of an IC without the requirement for fault coverage simulations or the calculation of probabilities. It would be further advantageous if such estimation could be performed as early as the RTL description phase of the design stage. With an estimate of achievable fault coverage available prior to fault simulations, the designer could decide whether to modify the design to make it more testable. An estimate of the theoretically achievable fault coverage could also be used as a standard against which test vector sets could be evaluated.